1. Field of the Invention
The present invention relates to a method of altering the distribution of a chosen characteristic of a plurality of memory cells forming a memory device.
2. Description of the Prior Art
As process geometries shrink in modern data processing systems, the variability in certain characteristics of the individual circuit elements increases. Considering as an example a memory device consisting of an array of memory cells, it will be understood that each memory cell will typically consist of a number of electronic components such as transistors, and the variability in those individual components significantly increases as process geometries shrink. To ensure correct operation of the memory device, it is typically necessary to control the operation of the memory device having regards to the worst case characteristics of the memory cells within the device.
Furthermore, there is an increasing desire to operate data processing systems at lower and lower supply voltages, and as the supply voltage decreases, reliability issues due to the variations in the individual components become more prominent.
One example of a characteristic which exhibits such variations is the minimum supply voltage required to ensure that a memory cell can correctly store a data value during a write operation, this characteristic being referred to herein as the write Vmin characteristic. A typical write Vmin distribution in a large memory array such as an SRAM array is schematically shown in FIG. 1 by the curve 10. As shown in FIG. 1, there is a relatively long tail region 20, and as process geometries shrink this tail region becomes longer.
Such Vmin distributions can be plotted for a variety of operations within the memory array, for example a write operation, a read operation, a data retention operation, etc. As process geometries shrink to sub-50 nm processes, it is typically the case that write operations are more susceptible than other operations to failure as voltage supply is reduced, and hence the actual minimum voltage that the memory array can be operated at is determined by the tail region of the write Vmin distribution. In particular, it is necessary to set as a minimum operating voltage a voltage that will enable all memory cells to operate correctly when subjected to a write operation.
The cause of write failures will be illustrated with reference to FIG. 2, which shows a typical 6T (six transistor) memory cell. As shown in FIG. 2, a latch formed by the interconnection of transistors 20, 25, 30, 35 is used to store a single bit data value. In particular, during a write operation, one of the bit lines 50, 55 will be driven to a logic one value whilst the other bit line will be driven to a logic zero value. At the same time, a write word line pulse will be provided to the access transistors 10, 40 to turn those transistors on and thereby connect the bit lines to the latch. For a successful write operation this will cause the nodes 60, 65 to be driven to opposite logic levels to each other, to thereby encode either a logic zero value or a logic one value within the latch, dependent on the values provided on the bit lines. At the end of the write operation, the pulse provided to the access transistor 10, 40 will be de-asserted, whereafter the written value will be retained within the latch.
However, FIG. 2 illustrates an example where the write is not successful. In particular it is assumed that the current state within the latch at the start of the write operation comprises a logic 1 value at node 1 60, and a logic zero value at node 2 65. For a normal write operation, one of the bit lines (in the illustrated example bit line 50) will push a “0” value and the other bit line (in the illustrated example bit line 55) will push a “1” value. Since the access transistors 10, 40 are NMOS devices, the side pushing a “0” dominates the write (in this case, the side with the BL bitline 50). Hence, the success of the write operation will depend mainly on the relative strengths of the pull-up PMOS and access NMOS transistors (in this case, the PL 20 and AL 10 transistors). The AL transistor 10 has to be stronger than the PL transistor 20 to ensure that the write operation succeeds. The bitline BLB 55 which is trying to push a “1” also impacts the write operation as a second order effect. In this case, the relative strengths of the NR 35 and AR 40 transistors are of importance.
For a memory cell in the tail region 20 shown in FIG. 1, a problem that can arise is that, once the supply voltage is reduced, the cell cannot be flipped during the write operation. This mainly happens due to intrinsic device variability where the pull-up PMOS transistor becomes much stronger than the access NMOS transistor such that the access transistor cannot force a new value onto the relevant node of the latch. In the example shown in FIG. 2, if the PL transistor 20 becomes much stronger (has a lower threshold voltage Vt, as an example) than the AL transistor 10, the node 1 60 will not flip to “0” during the write operation illustrated, since the PL transistor 20 will strongly keep the “1” value at that node 60 This is a problem which is exacerbated at lower supply voltages. Hence, the cells in the long tail region limit the voltage scaling range due to write failure issues, and thus put a limit on write Vmin.
Various write assist schemes have been proposed to improve the SRAM write-ability (and hence lower Vmin) For example the article by V. Chandra, C. Pietrzyk and R. Aitken, entitled “On the Efficacy of Write-Assist Techniques in Low Voltage Nanoscale SRAMs,” IEEE Design Automation and Test in Europe, March 2010, describes the various write assist techniques currently used in SRAM design and their trade-offs.
Effective write-assist schemes include wordline boosting and/or provision of a negative voltage bitline, which both serve to increase the strength of the access transistors relative to the transistors within the latch. Hence, considering by way of example the earlier write problem described with reference to FIG. 2, such approaches will increase the strength of the access transistor 10 relative to the pull-up PMOS transistor 20, thereby increasing writeability. However, the implementation usually requires a charge pump or other coupling based techniques to modulate voltage, both of which cause area increase. As an example, commonly owned copending U.S. patent application Ser. No. 12/591,751, the entire contents of which are hereby incorporated by reference, describes a wordline boosting approach that using a coupling based technique to modulate voltage. In addition to an undesirable increase in area, wordline boosting and negative bitline techniques can cause stability issues in half selected cells in a row (i.e. those cells subjected to an asserted wordline signal but which are not the addressed memory cells for the write operation) and in non-selected column cells respectively.
Another type of write assist scheme involves Vdd lowering and/or Vss raising, both of which weaken the transistors in the latch relative to the access transistors. These techniques are typically easier to implement with reduced area overhead when compared with wordline boosting or negative bitline techniques. However, the stability of bit cells is adversely impacted since the supply voltage or the ground nodes are modulated, thus resulting in reduction of noise margin.
Apart from the spatial variations described above with reference to FIG. 2, modern transistors also undergo temporal variations as well. As the regime of sub-45 nm technology node is entered, the stress in the devices causes them to age faster which reduces the life of the device in field. The reliability problem is touted as one of the most important concerns for future devices, see for example the article by S. Borkar entitled “Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation,” IEEE Micro, 2005, and the article by J. W. McPherson entitled “Reliability Challenges for 45 nm and Beyond,” IEEE Design Automation Conference (DAC), 2006. One of the major causes of an unreliable device is NBTI (Negative Bias Temperature Instability). NBTI is an effect where the PMOS devices get stressed at higher temperature when the gate-source bias is negative. The usual impact of NBTI is an increase in the device threshold voltage (Vt) over the life of the device. The degradation of device threshold can manifest as path delay failures. However, the shift in threshold voltage Vt is a function of the stress level on the device. A PMOS device which has a static “0” at its gate and a static “1” at its source is likely to get much more stressed than a device where the inputs (hence gate-source bias) change with time. The changing bias anneals the stress and hence it does not let the Vt degrade. A similar but reverse phenomenon happens for metal gate, high-k dielectric NMOS transistors. In this case, PBTI (Positive Bias Temperature Instability) stress impacts the NMOS devices in the design.
FIG. 3 illustrates the transistors undergoing NBTI and PBTI stress in a bit cell. In this case, the cell is holding a “1” at node 1 60 (and consequently a “0” at node 2 65). The cell could be contributing to the long tail 20 due to it being difficult to write to this cell at lower voltages. As explained above, this is due to the relative strengths of PMOS/NMOS transistors in the latch with respect to the access transistors. However, an interesting aspect to note is that the state which the cell is holding causes it to undergo NBTI/PBTI stress in such a way that it makes writing to the cell easier over time with aging.
By way of example, if the bias state and transistors in FIG. 3 are considered, the transistor PL 20 is holding a strong “1” at node 1 60. Similarly, transistor NR 35 is holding a strong “0” at node 2 65. These two transistors are strong and hence it is difficult for the AL and AR transistors 10, 40 to force a new state, as they would be trying to do during a write operation where bitline 50 is at a logic zero level and bitline 55 is at a logic one level. However, due to the way NBTI and PBTI work, the PL and NR transistors 20, 35 are undergoing NBTI and PBTI stress respectively. Due to these BTI stresses, the threshold voltage (Vt) of the PL and NR transistors will go up over time. The increase in Vt will make the PL and NR transistors weaker, thus making it easier to flip the state of the cell during the write operation. It should be noted that the NL and PR transistors 30, 25 do not have any BTI degradation in the state shown in FIG. 3, but would do so if the opposite state were strongly stored in the cell.
This potentially beneficial effect of BTI stress was recognised in the article by J. Wang et al entitled “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress,” IEEE Custom Integrated Circuits Conference, September 2010. The key idea in this article is to use the power-up state to provide an indication of mismatch in unbalanced memory cells and then use the power-up state as a BTI stress pattern. However, a potential problem with this approach is that even a minor mismatch in transistor strengths can cause a bit cell to power up in a particular state, but this does not mean that the cell needs to be stressed or improved. Hence, while more imbalanced cells may be healed by the BTI stress pattern, the originally more balanced cells may be deteriorated by over-stress. Although the paper seeks to limit this possibility by periodic re-power up of the device, there is still a significant likelihood that the process will cause detrimental effects in various cells, particularly those that were reasonably balanced prior to the BTI stress process being initiated.
Accordingly it would be desirable to provide an improved technique for altering the distribution of a chosen characteristic of a plurality of memory cells forming a memory device, such a characteristic for example being a minimum voltage required for a write operation.